1. Field of the Invention
The present invention pertains to the novel-volatile memory, more particularly to a programming circuitry for electrical erasable flash memories.
2. Description of the Prior Art
In recently years, the development of the portable telecommunications and laptop computers has become a major driving force in semiconductor IC's design and technology. This growing market requires low power, high-density and electrically re-writable nonvolatile memories. Electrically erasable programmable read only memories (EEPROM) which are electrically erased on a byte-by-byte basis is one choice; however, its cell size is too large for application, and thus flash memory is another choice because of its small size and highly reliability. A typical prior art circuitry for programming an electrical erasable flash memory is best illustrated by reference to the drawings.
FIG. 1 shows a simplified split gate flash memory cell, which is programming by a source-side channel hot electron injection mode (CHEI). A n+ region, which functions as the source 10 and another n+ region, functions as the drain 20 are formed in the silicon substrate. The control gate 30 via a word line connect to the periphery circuit, at the same time, a bit line 22 connects to the drain 20 and the periphery circuit. In order to program the cell, i.e. electrons via CHEI effects from the drain 20 into the floating gate 25, a high voltage V.sub.SL +11V is connected to the source 10. A threshold voltage V.sub.T, for example, +2V is applied to a control gate 30, at the same time; the voltage of the bit line 22 is demanded to drop to about V.sub.SS. The electron current will begin flow from source 10 toward drain 20 through the weakly inverted channel. When the electron flow see the steep rise voltage potential on the floating gate 25. The electrons be accelerated and become heated. Some of them will be injected through coupling oxide 28 and into the floating gate 25 until the potential drop on the floating gate 25 unable to sustain an induce surface channel right beneath the floating gate 25. If the floating gate 25 store with negative charges, as will be understood by those skilled in the art, the accumulation of a large quantity of trapped charge on the floating gate 25 will cause the effective threshold voltage of the transistor to increase. If this increase is sufficiently large, the transistor will remain in a conductive "off" state. When a predetermined read voltage is applied to the control gate 30 during a read operation (i.e. V.sub.T &gt;Vread), and thus it is said that the cell is in the programmed state of "0". On the contrary, if the bit line 22 voltage is maintained to about Vcc, the charge current into floating gate is weakly occurred, and thus it is in the programming state of "1".
FIG. 2a shows functional blocks of a circuitry for programming a forgoing flash memory cell in accordance with the prior art. A data input means 40 having a data signal input terminal DIN to receive data signal and a programming signal input terminal PROG to receive a programming signal, and an output terminal of data input means 40 is coupled with switch means 50. Switch means 50 is then couple with a decoder 60 and a discharge control circuit 55. FIG. 2b shows an example of a memory cell 70 in memory array 700, which is arranged in a series of rows and columns. The memory cell programmed is selected by a column decoder 100 and a row decoder 200. The equivalent circuitry to functional blocks for programming a forgoing flash memory cell 70 is shown in FIG. 2c. The switch means 50 comprise a CMOS transistor being coupled with a NMOS transistor MN3. After the PROG terminal receives a programming "start" signal (i.e. at voltage high state), the switch means 50, allow the data signal received by data input circuit 40 to achieve the addressed memory cell 70(selected by decoder means 60).
Before programming, the gates voltages of transistors MN6 and MN7 are set, respectively to case 1: V(W-L)=0, V(V-L)=V.sub.CC or case 2:. V(W-L)=V.sub.CC, V(V-L)=0 to pre-charge the bit line 22 of the memory cell 70 to V.sub.CC -V.sub.T. it is noted that the voltage of terminals W-L and V-L are set, respectively to be complementary to the terminals of W and V of transistors MN4 and MN5. In programming the "0" state, set V(W-L)=V(V-L)=0, firstly, and then the transistors MN4 and MN5 serves as a column decoder 60, which are responsive to a voltage V.sub.CC on input terminals V and W, respectively, to address the memory cell 70. In decoder circuit 60 that includes transistors MN4, MN5, MN6 and MN7 is a portion of column decoder 100. Please see FIG. 2a-2b. The memory celf 70 is requested at a ready state in order to program. For example, the source line 12 and the word line 32 of the memory cell 70 are applied, respectively to voltages of 11V and V.sub.T. On the other hand, since before the program commence the voltage of the terminal W is V.sub.CC, hence the bit line 22 voltage pre-charge to a level V.sub.CC -V.sub.T (V.sub.T is the threshold voltage of transistor MN6). The bit line 22 voltage will be demanded to discharge by the programming current I.sub.PROG through the discharge control block 55, wherein the discharge control block 55 is a MOS transistor MN1 that biases by a voltage of V.sub.BIAS until the bit line 22 voltage decreased to about 0.6 Volt. It will take a lot of time to discharge the bit line 22. For example if the conditions are set as following: V.sub.CC =5V, V.sub.T =0.8V, the bit line loading 24 is 2 pF, and the typical programming current is I.sub.PROG =1 .mu.A. It will spend about 6 .mu.s (it depends on the memory size) to discharge the bit line 22 voltage. Therefore, for programming large memories, in addition to charge the floating gate 25, it will totally require a quite obvious extra time to discharge the bit line 22.